1. Technical Field
The present invention generally relates to a semiconductor integrated circuit and to a data output circuit.
2. Related Art
Among semiconductor integrated circuits, a semiconductor memory apparatus refers to an apparatus which receives and stores data and outputs stored data. Thus, the semiconductor memory apparatus includes a data output circuit for outputting data.
FIG. 1 shows a conventional data output circuit of a semiconductor memory apparatus.
A conventional data output circuit 1 is configured to drive internally stored data D_in in response to an on-die termination code ODT_code<0:3> (i.e., ODT_code<0>, ODT_code<1>, ODT_code<2>, ODT_code<3>) provided from an external controller and a calibration code cal_code<0:2> (i.e., cal_code<0>, cal_code<1>, cal_code<2>) provided from an internal calibration circuit and generate data D_out to be outputted to an outside. The on-die termination code ODT_code<0:3> and the calibration code cal_code<0:2> are codes to compensate for impedance mismatch between a semiconductor memory apparatus and an external circuit (controller). The calibration code cal_code<0:2> includes a P code Pcode<0:2> (not illustrated) and an N code Ncode<0:2> (not illustrated).
The data output circuit 1 includes first to fourth driving units 10, 20, 30 and 40.
The first driving unit 10 includes a first pre-driver 11 and a first main driver 12.
The first pre-driver 11 is configured to drive the input data D_in according to the first bit ODT_code<0> of the on-die termination code ODT_code<0:3> and generate first pre-pull-up data pre_data_up<0> and first pre-pull-down data pre_data_down<0>.
The first main driver 12 is configured to drive the first pre-pull-up data pre_data_up<0> and the first pre-pull-down data pre_data_down<0> according to the calibration code cal_code<0:2>, and transfer resultant data to an output node Node_out.
The second driving unit 20 includes a second pre-driver 21 and a second main driver 22.
The second pre-driver 21 is configured to drive the input data D_in according to the second bit ODT_code<1> of the on-die termination code ODT_code<0:3> and generate second pre-pull-up data pre_data_up<1> and second pre-pull-down data pre_data_down<1>.
The second main driver 22 is configured to drive the second pre-pull-up data pre_data_up<1> and the second pre-pull-down data pre_data_down<1> according to the calibration code cal_code<0:2>, and transfer resultant data to the output node Node_out.
The third driving unit 30 includes a third pre-driver 31 and a third main driver 32.
The third pre-driver 31 is configured to drive the input data D_in according to the third bit ODT_code<2> of the on-die termination code ODT_code<0:3> and generate third pre-pull-up data pre_data_up<2> and third pre-pull-down data pre_data_down<2>.
The third main driver 32 is configured to drive the third pre-pull-up data pre_data_up<2> and the third pre-pull-down data pre_data_down<2> according to the calibration code cal_code<0:2>, and transfer resultant data to the output node Node_out.
The fourth driving unit 40 includes a fourth pre-driver 41 and a fourth main driver 42.
The fourth pre-driver 41 is configured to drive the input data D_in according to the fourth bit ODT_code<3> of the on-die termination code ODT_code<0:3> and generate fourth pre-pull-up data pre_data_up<3> and fourth pre-pull-down data pre_data_down<3>.
The fourth main driver 42 is configured to drive the fourth pre-pull-up data pre_data_up<3> and the fourth pre-pull-down data pre_data_down<3> according to the calibration code cal_code<0:2>, and transfer resultant data to the output node Node_out. The voltage level of the output node Node_out is outputted as the output data D_out being the output of the data output circuit 1.
FIG. 2 shows the first pre-driver 11 and the first main driver 12 of the first driving unit 10.
The first pre-driver 11 includes a NAND gate ND1, a NOR gate NOR1, and first and second inverter chains 11-1 and 11-2, respectively. The NAND gate ND1 is inputted with the first bit ODT_code<0> of the on-die termination code ODT_code<0:3> and the input data D_in. The NOR gate NOR1 is inputted with an inverted signal ODT_codeb<0> (i.e., through IV1) of the first bit ODT_code<0> of the on-die termination code ODT_code<0:3> and the input data D_in. The first inverter chain 11-1 is inputted with the output of the NAND gate ND1 and outputs the first pre-pull-up data pre_data_up<0>. The second inverter chain 11-2 is inputted with the output of the NOR gate NOR1 and outputs the first pre-pull-down data pre_data_down<0>.
The first main driver 12 includes first to twelfth transistors P1 to P6 and N1 to N6, respectively. The first transistor P1 has a gate which is inputted with the first bit Pcode<0> of the P code Pcode<0:2> and a source to which an external voltage VDD is applied. The second transistor P2 has a gate which is inputted with the first pre-pull-up data pre_data_up<0>, a source to which a drain of the first transistor P1 is connected and a drain to which the output node Node_out is connected. The third transistor P3 has a gate which is inputted with the second bit Pcode<1> of the P code Pcode<0:2> and a source to which the external voltage VDD is applied. The fourth transistor P4 has a gate which is inputted with the first pre-pull-up data pre_data_up<0>, a source to which a drain of the third transistor P3 is connected and a drain to which the output node Node_out is connected. The fifth transistor P5 has a gate which is inputted with the third bit Pcode<2> of the P code Pcode<0:2> and a source to which the external voltage VDD is applied. The sixth transistor P6 has a gate which is inputted with the first pre-pull-up data pre_data_up<0>, a source to which a drain of the fifth transistor P5 is connected and a drain to which the output node Node_out is connected. The seventh transistor N1 has a gate which is inputted with the first bit Ncode<0> of the N code Ncode<0:2> and a source to which a ground terminal VSS is connected. The eighth transistor N2 has a gate which is inputted with the first pre-pull-down data pre_data_down<0>, a drain to which the output node Node_out is connected and a source to which a drain of the seventh transistor N1 is connected. The ninth transistor N3 has a gate which is inputted with the second bit Ncode<1> of the N code Ncode<0:2> and a source to which the ground terminal VSS is connected. The tenth transistor N4 has a gate which is inputted with the first pre-pull-down data pre_data_down<0>, a drain to which the output node Node_out is connected and a source to which a drain of the ninth transistor N3 is connected. The eleventh transistor N5 has a gate which is inputted with the third bit Ncode<2> of the N code Ncode<0:2> and a source to which the ground terminal VSS is connected. The twelfth transistor N6 has a gate which is inputted with the first pre-pull-down data pre_data_down<0>, a drain to which the output node Node_out is connected and a source to which a drain of the eleventh transistor N5 is connected.
The second to fourth driving units 20, 30 and 40 have the same configuration as the first driving unit 10 configured in this way except that their input signals are different.
In the first main driver 12 illustrated in FIG. 2, in order to drive the output node Node_out, the transistors which are inputted with the P code Pcode<i> and the first pre-pull-up data pre_data_up<0> are connected in series, and the transistors which are inputted with the N code Ncode<i> and the first pre-pull-down data pre_data_down<0> are connected in series. Thus, in order to drive the first to fourth main drivers 12, 22, 32 and 42 illustrated in FIG. 1, the first to fourth pre-drivers 11, 21, 31 and 41 should have large driving forces.
As a result, in the conventional data output circuit, since loading of the main drivers is substantial, current consumption increases and this is inappropriate for high speed operations.